1. Field of the Invention
The present invention relates to semiconductor field, and more particularly, to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In MOS devices, improving carrier mobility can increase driving currents for MOS devices and improve device performance, and therefore, carrier mobility enhancement techniques have been widely studied and used.
An effective mechanism for improving carrier mobility is to produce stress in the channel region. Generally, the channel region of a NMOS device can be applied with tensile stress to improve its electron mobility, and the channel region of a PMOS device can be applied with compressive stress to improve its hole mobility. Embedded SiGe techniques have been widely used in modern CMOS technique, which can apply compressive stress to the channel region by way of embedding SiGe material having compressive strain into the source and drain regions of a PMOS device, so as to achieve significant performance improvement for the PMOS device.
In embedded SiGe techniques, commonly, the effectiveness can be enhanced through, for example, raising the content of Ge, in-situ boron (B) doping, stress proximity (closer to the channel) and the like. However, these techniques may bring many challenges and issues for process and integration. For example, a high content of Ge may result in much worse defects in the SiGe material; closer to the channel requires smart integration of reactive ion dry etching, isotropic wet etching and optimized epitaxial growth; and so on.
Therefore, a new technique is desired for further enhancing compressive stress in the channel region of a PMOS device having an embedded SiGe structure. A method of enhancing channel stress is described in the paper of S. Natarajan et al, “A 32 nm Logic technology featuring 2nd-generation High-k+Metal-Gate Transistors, Enhanced Channel Strain and 0.171 um2 SRAM Cell Size in a 291 Mb Array” (IEEE International Electron Devices Meeting 2008 (IEDM2008) Technical Digest, Pages: 941-943). FIGS. 1A-1C are diagrams from that paper showing the increased stress in a replacement metal gate (RMG) process flow. As shown in FIGS. 1A-1C, when the gate is filled with polysilicon 102 serving as dummy gate material, the SiGe 104 embedded in the source/drain regions may apply a certain compressive stress to the channel region (FIG. 1A); compressive stress applied to the channel region is enhanced upon removing the polysilicon in the gate (FIG. 1B); and then a metal gate 106 is deposited, and at that point, the increased compressive stress has been maintained (FIG. 1C). Thereby, this method further increases channel compressive stress on the basis of embedded SiGe techniques.
Nevertheless, with the continuous development of semiconductor techniques, there is always a need for a technique capable of further enhancing channel stress.